VLSI Architecture Design Of CABAC Encoder In H.264

The rapid development of information technology has brought human into a brand-new information society. With the evolution of video compression coding, especially the appearance of H.264 as a new generation video coding standard, it enhanced the area of video applications. At the same time, computer and IC technology has also developed very quickly, and the processing speed of hardware platform has improved remarkably, which lay the foundation for real-time video applications.Entropy coding is a key technology of H.264 standard, including two basic coding methods: Context-based Adaptive Variable Length Coding (CAVLC) and Context-based Adaptive Binary Arithmetic Coding (CABAC). This paper mainly research on CABAC entropy coding in H.264 main profile. Because encoding a single binary symbol using CABAC requires a great deal of computation, including binarization, context model selection, binary arithmetic coding and context model update, it is very difficult to achieve real-time HD video coding through software implementation. Therefore, it is of great significance to design a CABAC hardware architecture. However, the bit serial processing and complicated data dependency of CABAC algorithm makes it extremely difficult to parallel processing. So, this paper presents a highly efficient hardware of CABAC encoder, under the carefully research and analysis of CABAC algorithm.This paper firstly makes a brief introduction on H.264 Codec architecture and its key technologies. Secondly, it makes a carefully research and analysis of CABAC algorithm. Thirdly, it presents a highly efficient hardware of CABAC encoder from system architecture scope, and makes a detail introduction on four mainly functional modules, including encoding sequence controller, MB context management, binarization and context modeler, and binary arithmetic coder. Finally, the paper introduces the design and verification method of the CABAC encoder, and analyses the results of simulation and synthesis. Simulation results and performance analysis show that the proposed architecture can meet the requirements of real-time HD 1920×1080@30f video encoding.