A High Performance Hardware Implementation Method For NoC Routing Algorithm

New tendencies envisage multiprocessor systems-on chips (MPSoCs) as a promising solution for the high performance embedding system. And the key challenge is how to improve the communication efficiency. Network on Chip (NoC) has been considered as a new paradigm in the next generation communication architecture due to its extensibility and power efficiency. By now a significant amount of theoretical work has been done exploring various NoC routing algorithm. But only a few studies have demonstrated actual implementation of NoC-based systems for routing algorithm.In the traditional implementation method, all of the routing information including every step is stored in the header of the packet, so the packet length is very long which lead that the latency and power consumption are greater and throughput are lower. In this paper, we propose a new hardware implementation method to implement the routing algorithm for NoC, which can reduce the packet length and simplify the router architecture and achieve the purpose of effectively minimizing the latency and power consumption and increasing the throughput.The proposed prototype is implemented on Altera Stratix II FPGA device. The experiment results show that the proposed method uses less resource than the traditional one. especially the number of ALUT. We also can see that the smaller recourse is not just for only one routing algorithm implementation. The X-Y routing algorithm, WestFirst routing algorithm, NorthLast routing algorithm and NegativeFirst routing algorithm, all of the recourse of them is smaller than the traditional method. We use a cycle accurate simulator to evaluate the performance of the proposed network on 5x5 NoC. From the results we can see that the NoC prototype of our proposed method implementation for routing algorithm is effective in latency, power consumption and increasing throughput.