Study Of Threshold Voltage And Reliability Of Strained PMOS Device By Simulation

Strained Si technology introduces stress to the channel of MOS devices by using appropriate process or materials. The band structure of Si, the conductivity effective mass and the carriers'scattering probability can be altered by stress, resulting in the favorable increase of carriers'mobility. Due to the good effeciency in improving the device performance, the strained Si technology has acquired focused research and successful applications in semiconductor industry. Current research efforts are more concentrated on the methods to introduce stress to the devices, process improvement, and developing novel device structures.Recently, wide attention has been paid to the effects of strain on electrical parameter models, as well as the stability and reliability of these novel devices, for example, the threshold voltage model of strained MOS with SiGe substrate, the off-state leakage current and the gate-induced drain leakage current (GIDL), the bias temperature instability (BTI). When the carriers'mobility increases with increasing channel stress, the high doping concentration, the thin gate oxide thickness and the short channel length of stained MOS devices may increase the leakage current, and deteriorate the stability of such devices.Based on the detailed analyses of Si/SiGe parameters, such as the band structure, density of states, intrinsic carrier concentration and Ge molar fraction, this thesis studies the factors influencing the threshold voltage of strained PMOS with SiGe source/drain (S/D) first by solving one-dimensional and two-dimensional Poisson's equations. Results are also verified by the TCAD tool Sentaurus. Furthermore, the relation between the short channel effect and the Ge molar fraction is studied by solving the Poisson's equation using the variation method. The effect of Ge molar fraction on the device stability is also discussed. Results indicate that the threshold voltage decreases with increasing Ge molar fraction. The channel length and the applied drain-source voltage of strained PMOS are also important influencing factors of the threshold voltage, while the Ge molar faction has a minor effect on the short channel effect.Moreover, the TCAD tool Sentaurus Process is applied to the process simulation of a uniaxial strained Si PMOS device with 50 nm gate length fabricated using Intel's 90 nm processing technology. The original electrical simulation results from Sentaurus Device are calibrated according to the reported experimental data. The off-state leakage current and GIDL current are then studied by simulation. With increasing Ge molar fraction, the channel stress increases, resulting in the higher hole mobility and thus the larger valence band difference between SiGe and Si, and finally the increasing off-state leakage current. On the contrary, GIDL current decreases with increasing Ge molar fraction, and is easier to generate at higher applied drain-source voltage. Finally, the BTI degradation which has a severe effect on the life of deep sub-micron MOS devices is simulated. The results show that the NBTI degradation of strained PMOS is worse than that of bulk Si device. Increases of both the temperature and the diffusion rate of hydrogen in oxide can lead to severe NBTI degradation.