| Due to the advantage of high luminous efficiency, long life, small size and environmental protection, white LED have been widely used in mobile phones, digital cameras, MP4 and portable computers and other portable electronic products. In recent years, increasing PC penetration, consumer electronics constantly upgrading, drive to promote white LED production soared. To meet the wide range of market demand, the world's major semiconductor companies have developed variety of high performance white LED driver. Design of white LED driver IC has become a research hotspot in power management chip market.This paper designed a DC-DC boost chip with PWM controlling mode that can be widely used for display backlighting of many portable products. The chip used the dual-loop feedback controlling mode and peak current detecting methods, in the range of 3~6 volts fo input voltage, the constant output current is 300mA, can steadily drive a group of 3 white LEDs in series. The chip has a high-power switch MOS, an oscillator of 1.2MHz frequency, a PWM comparator, a band-gap voltage reference, and so on. The chip has been designed by the standard of CSMC 0.5um two-polysilicon, triple-metal CMOS process.This paper introduced the application of the white LEDs, the research status of the white LEDs driver, and then described the basic structures, the working principles, the advantages of the PWM controlling mode, and proposed the targets of this chip. According to the targets, designed the overall structure of the chip, and divided it into several sub-modules. Make use of Cadence to complete the design and simulation about each sub-module, focused on analyzing the band-gap voltage reference, oscillator and slope compensation module. On these bases, selected the appropriate external device models, the chip had made the overall simulation of voltage and transient performance. The results showed: in the 3V, 4.2V and 6V, under the tt and ff process corners, the output voltage was 12V, output current was 300mA, ripple value of the fluctuations was below 2%; under the ss process corners, the maximum of output voltage and output current and was only 11V and 280mA, can not meet the design requirements; under the three processes, its start-up time was less than 200μs; under a typical voltage of 4.2V, the power conversion efficiency was 65.8%.Finally, depended on Cadence's Virtuoso Layout Editor design tools and Assura layout verification tool to complete layout design, DRC, LVS verification and post-simulation. |