Research Of A Zero-Crossing-Based Pipelined ADC

As a general analog-to-digital interface, ADC is widely used in mixed signal circuits. Due to the development of digital signal processing technology and integrated circuit technology, analog-digital converter is developing to the phase of higher performance, such as higher conversion speed, higher precision, lower power dissipation, smaller area, and so on.Pipelined ADC is widely used because it has a good balance between speed, precision and power consumption. It can achieve both high conversion speed and high precision. Sample and hold circuit is an extremely critical module of a pipelined ADC. Its precision and speed has a great influence on the performance of the whole system. With the decreasing size of integrated circuit technology, the device gain and voltage supplies are decreasing. Designing a high gain, high-speed op amp becomes more and more difficult, which increases the difficulty of realizing a precision charge transfer in the traditional manner via a high-gain, high-speed operational amplifier in feedback. This work proposes a novel sample and hold circuit which is called zero-crossing-based sample and hold circuit. It is fast, simple and it avoids designing the high-gain, high-speed op amp. And it realizes the same charge transfer as opamp-based circuit.In this paper, the basic of the pipelined ADC is firstly analyzed. Then, in cadence design environment, based on SMIC 0.18um CMOS model, the paper designs and simulates the circuits which consisted in pipelined ADC, such as CMOS analog switch, zero-crossing circuit and comparator. The zero-crossing-based sample and hold circuit is simulated under the conditions of power supply of 1.8V, input sinewave with frequency of 1.9938MHz and amplitude of 0.15V, the sampling frequency is 40MHz, the simulated results show that the settling time is 5 ns, the spurious free dynamic range (SFDR) is 58.12dB, the power dissipation is 300.88uW. It can be used in 6-bit 40MHz pipelined ADC. It gives a new way of thinking about the sample and hold circuit. Then, the paper designs and simulates the MDAC circuit, sub-ADC circuit and the single stage circuit of the zero-crossing-based pipelined ADC. At last the layout and post simulation of the sample and hold circuit are carried out in this paper.