A Rubidium Atomic Frequency Standard Chip Design Based On Direct Digital Frequency Synthesizer

As reference of frequency and time, the rubidium atomic frequency standard (RAFS)is vastly used in the field of navigation, communications, missile, astronomical observation, given time, instrument calibration etc., and the accuracy of corresponding applications is directly determined by its performance. With the development of very large scale integrated circuit technology, more and more complex circuits can be integrated into a chip. By integrating the servo circuit of the rubidium atomic frequency standard into a chip, the routing complexity, the volume and the power dissipation can be effectively reduced, and the frequency accuracy and the frequency stability of the rubidium frequency standard output signal can be greatly improved.In this dissertation, the operational principle of passive RAFS is analyzed and a passive rubidium atomic frequency standard structure with servo circuits suitable for integration is presented and selected, and the servo circuits chip for this kind of rubidium frequency standard is implemented by using CMOS process. The chip includes a compact direct digital frequency synthesizer with 32-bit phase storage depth and a 10-bitcurrent steering digital to analog converter.The operational principle of passive rubidium atomic frequency standard is analyzed in detail, and two kind of passive rubidium atomic frequency standard with servo circuits suitable for integration is presented. A passive rubidium atomic frequency standard is adopted and its servo circuit is integrated into a chip using CMOS process.A compact direct digital frequency synthesizer (DDFS) used for System-on-Chip implementation of high stability rubidium atomic frequency standards is presented and developed in this paper. The phase to sine mapping data is compressed by using sine symmetry technique, modified Sunderland technique, sine-phase difference technique quad line approximation (QLA) technique and quantization and error read only memory(QE-ROM) technique, thus the chip area is greatly reduced and the power consumption is lowered. The ROM size is reduced by 98% using the techniques mentioned above. A compact DDFS chip with 32-bit phase storage depth and a 10-bit on-chip current steering digital to analog converter (DAC) has been successfully implemented using standard 0.35μm CMOS process.