The Research And Design Of Low-Noise Low-Power LDO

In recent years, power management technology has became more and more important with the rapidity development of the electronic produces. At present, LDO are most widely used within many kinds of the power management chips. This is because of the low input/output voltage of the LDO and there are several advantages such as low ripple and low output noise. Such character can meet the need of voltage transformation.Besides, the small chip area and the relatively simple external circuit is conducive to miniaturization and lightness of the electronic products. Because of these,LDO are suitable to the portable electronic products such as PDA,MP3,MP4,digital camera, mobile phone which have been developed rapidity in decades. Therefore, researching the high-performance LDO is clear and practical importance.Based on the CSMC 0.5um CMOS process, variety methods which can reduce noise and power consumption are used in this paper to design a new type of LDO. Such chip has a widely input voltage range between 3.5V and 5.5V, a regulated output voltage which is 3V, what is more, the maximum current is up to 150mA,linear adjusted range is 0.8mV/V, power supply rejection ratio is 64dB, the static current is less than 150uA. Therefore, the LDO which is design in this paper can apply to the portable electronic products under the harsh condition.Firstly, this paper describes the current situation and development of the power management chips and LDO briefly. Analysis the basic principles and performance of LDO and the specifications of LDO are indicated in the paper. Secondly, each module of the LDO is described in detail,including principle analysis, circuit designed and simulation test result. The band gap voltage reference module is used the technology which have no relationship with the power to design the start up and bias circuit in order to ensure the accuracy and stability of the reference voltage. In the error amplifier module, the nested Miller frequency compensation technology and the dynamic zero compensation techniques are applied make sure that the PSRR of the LDO is improved. In the over-temperature protection module using the temperature differential comparison technology and the windows hysteresis technology to ensure the chip can work in the over-temperature situation. Then, making overall simulation and layout designed to the LDO. The results of the chip occupied an area of 823um*635um. Finally, simulation and test results show that the development of the chip can meets the need of the specification requirements.