Research And Implementation Of Core Module In ARM Based On FPGA

To improve the efficiency of ARM processor, the analysis and research of the system architecture and the instruction system are done firstly in this paper. Then the havard architecture is applied to the Arm7 embedded processor, in which the data bus and the instruction bus are separated. And the Harvard aechitecture can ganrantuee the spatical and time parallism in the ARM embedded processor. Secondly, the intensive study of some core module in ARM is done, such as the interrupt vector table (IVT) and the micro program controller. Then the controllable abnormity table (CAT) and the micro program controller with reconfigurable system instructions (MCRI) are introduced here. Finally, the design with Top-Down meathod and the Hardware Laguage of Verilog is proposed in the paper. And the design of the CAT, the instruction decoder, and the MCRI is finished with FPGA-oriented EDA development mode in the Xilinx ISE 9.1i. Then the simulation of above design is performed in ModelSim XE III 6.2c.The abnormity table is the key of the development of the embedded system, and it is derived from the IVT in ARM by improve the next two respects. On the on hand, instead of the relationship of mapping with two levels, the tree structure with three levels in depth is applied in the CAT and used for describing the CAT and every processing branches of abnormity. Then the controllability of the CAT can be realized by changing the processing branches. One the other hand, the respond speed and the processing efficiency of abnormity both are improved by integrating the arbitration controller into the CAT.The micro program controller is the key of ARM processor. By analysing the fuction and structure of the micro program controller, the MCRI is introduced to improve the application of the onefold instruction system. Then the MCRI is realized by the danamic micro-program design mode, and the instruction system is more flexible. Thus, the fuction of the instruction ande the system instruction set both are can be changed according to the applications.The instruction decoder (IR) is quite important to the micro program controller. Based on the study and research of IR, the fuction of simple decoding is added to the IR. Then the IR not only can separate the opcodes and the operation data from the instructions, but also can decode the operation data address. So the IR can speed the data pipeline by putting out the operation data to the addressing device.To prove the stability of the improved prodessor, the simulation of circuit of above modules is done in the ModelSim. And the results implement that the flexibility and the system efficiency can be improved by the improved core module in ARM. Moreover, the next three respects also can be verified: (1) The CAT can process abnormity efficiently, and the controllability can be realized by change the processing branch of the abnormity. (2) The instruction decoder not only can separate the opcode and the operation data correctly, but also can do some simple decoding. (3) The MCRI not only can be compatible with the Thumb instructions of ARM7, but also can realize the separation and the time parallelism of the instruction pipeline and the data pipeline. Then, the performance of system and the efficiency of processing instruction are improved. Then, with the extension and the expansion of the above designs, it is can be realized the embedded processor with high performance and high efficiency.