Design Of Fault-tolerant Router In Network On Chip

Network on Chip (NoC) , as a new proposed solution to solve global communication problem in complex System on Chip (SoC) design,has been widely accepted by researchers. In addition to providing high performance, the fault-tolerance is becoming a critical issue in NoC-based Multi-Processors SoCs (MPSoCs) design. NoC gives us an opportunity to solve one-point fault problem as there are enough redundant links between two nodes to reconfigure the communication system. However, a faulty node or link will make the micro-network topology irregular. Therefore, the routing algorithm must be reconfigured to adapt to the modification of the micro-network topology. Besides, deadlock and livelock problem will be more trickiness in irregular topology. Moreover, the realization of fault-tolerance is generally at the cost of performance, which makes it challenging to fulfill faullt-tolerance while achieve high performance.Based on the worldwide research work of fault tolerant mechanism, this paper presents a new fault model of NoC which defines both node-fault and link-fault and as a result reduces situations counted as node-fault. Based on the fault model, we present a deadlock-free routing algorithm for a 2D-Mesh Network-on-Chip dedicated to fault-tolerant, which can be dynamically reconfigured to adapt to the modification of the micro-network topology caused by a faulty router or a faulty link.Followed with the IC design flow, we present two router architecture designs adapted to different network load. One is based on Virtual-Channel to make a target of high performance, adapted to high network load; and the other makes a target of low cost, adapted to low network load. Both routers adopt wormhole routing, credit-based flow control, oldest-first priority scheme and implement our fault tolerant routing algorithm.In the end, we used the cycle-accurate SystemC simulation model to evaluate the performance degradation of a 4×4 micro-network when it's topology is modified caused by a faulty router or a faulty link; we also compare the performances of our two routers in a 5×5 micro-network. Moreover, We used the HeJian standard cell library for a 0.18μm CMOS technology, and the Synopsys synthesis environment to evaluate the cost of our two routers from the point of view of the silicon area.