Research And Implementation On Parallel Storage Technique In Multi-bank Flash

In recent years, as computing technologies are developing, problem scales have been expanded constantly. More and more applications are pone to become data-intensive applications. The mechanical hard disks adopted by traditional storage systems are not competent for these kinds of applications any more. They have become the bottleneck gradually due to their high latency. However, as a pure electrical storage media, NAND flash memory is nonvolatile. Moreover, it has low I/O latency and high bandwidth. For the last decade, NAND flash memory has been improved once and again. Its drawbacks have been overcome gradually. NAND flash memory is replacing hard disks due to its excellent performance. Since NAND flash memory attracts more and more attentions, it has been widely studied. Related research issues include decreasing the I/O latency, increasing the bandwidth, exploiting the parallelisms between multiple ways, and so on.In this paper, the main work is that the parallel strategy is developed on a new type of solid-state disk design architecture: Meteoric structure, using a three multi-level organizational structure to improve the performance of Flash memory access storage array. First, we design the each function component on multi-bank NAND Flash parallel memory controller in detail, making single controller can send control commands to several chip simultaneously; second, we use a crossbar switch module Flash memory controller on the multi-control, multiple I / O requests to each memory module on schedule to achieve the system's switch-level parallelism; then we study the multi-bus parallel technique and super-chip control operations to improve the average memory access bandwidth of the request, proceed the bus-level parallel scheduling; Finally, we design the Agent unit to execute chip-level parallel scheduling, using chip-level interleaving access operation to reduce various types of the average delay to reach the purpose of the chip-level parallelism. On account of parallel memory system, the clock accuracy simulation results show that: Using two level parallel strategy makes the performance promotion nearly 6 times; after adding chip-level parallel, the performance promotion exceeds 7 times, the parallel strategy makes the overall performance large promotion.