The Research And Implementation Of Adaptive Viterbi Decoding

With the development of modern communication technology, high speed and high stability have come into being two key factors when measuring the quality of information tansmission. The technology of channel encoding, which can control the channel errors, reduce the code error rate, and ensure the stable communication, has a deep meaning in military affairs and civil applicaton. The Viterbi decoding algorithm and the methd of its implementation are important parts of the channel encoding. However, they have their own limitation as well. In the algorithm of Viterbi decoding, while the performance of decoding is improved with the increasing of length of the convolutional encoding , the complexity to implement it increases at the rate of 2k . This paper aiming at reducing the implemental complexity and increasing the decoding speed, does a research on the Viterbi decoding algorithm and the design of the decoder.Researching the Viterbi decoding algorithm as a foundation, This paper does a deep research on the key factors that have effects on the performance of decoding and the complexity of the algorithm's implementation. In allusion to the uneasiness to decide the vaule t in the t-algorithm adaptive Viterbi decoding and the bad performance to adaptive the applicable condition of vaule t , a modified Viterbi decoding arithm IAVA is put forward. In the algorithm, while a SNR evaluating module is utilized to automatically adjust the gate-vaule, a complexity evaluating module is used to automatically adjust the decoder's radix mode, through which, the resource is reasonably used. When working at the condition of low SNR, the gate-vaule is increased automatically. This way, reduces the decoding complexity while ensuring the good performance at the same time. When working at the condition of high SNR, the gata-vaule is decreased automatically to reduce the decoding complexity. In this working condition, the decoding mode is changed to radix-4 mode, which resultes in a rapid improvement in the decoding speed. As the emulating experiment shows, when the SNR is about 2.5dB, the decoding complexity decreases to half of the typecial decoder's decoding complexity with no obvious decrease of the decoding proformance. When the SNR is about 4dB and the decoding mode is changed to the radix-4 mode, the decoding proformance gets lower comparing with the typical decoder, but the code error rate is still low. All the results show that, this algorithm has a good performance in the condition of wide dynamic SNR.At the end of the paper, utilizing the FPGA platform, the IAVA decoder is desgned and the simulating platform is built, which has given the overview design and the module design. At last, the algorithm is validated based on the data gotten from experiment in the condition of different SNR. The result shows that, the algorithm has a good performance on adjusting the environment.