| Good input character, including good harmonic restrain ability and high power factor corrector is a very important purpose to show the high performance and high efficiency of UPS. The technology of the dual-Boost Active Power Factor Corrector (APFC) is the emphases of this thesis. And the purpose is to study a high performance digital controlled APFC. Firstly, the average current controlled APFC which is implemented by UC3854 is studied. The multiplier can be considered a proportion loop in low frequency bandwidth (low than 30Hz), so using a proportion-integral corrector can realize no static state error for the step disturb signal, and we add a pole point to decline the high frequency disturb after the cut-up frequency point. The object of the current loop can be considered a integral loop in high frequency bandwidth, and we use a proportion -integral corrector too, to realize no static state error for the speed disturb signal, a pole point is added for the same reason. Secondly, on the base of the dual-loop controller we have designed, we digitalize them, and use TMS320F2812 to implement digital control, which is used to control the inverter too. Since the profoundly influence of the delay in digital controller, the cut-up frequency can not be very high, and this make the dynamic performance very bad, sometimes, the steady performance of the system is influenced too. So a new control method, feed-forward and feed-backward control method is used for compensation. Thirdly, since the ripple voltage of the bus capacitor on the UPS which is three phase input and one phase output is very high, this influents the input character worse, so some improvement is done, includes a digital filter for the voltage error and a three phase current balance controller in voltage loop, the experiment result proves it very useful too. Finally, the experiment result is shown to prove that the digital control methods have been used can realize good harmonic restrain and high power factor. |
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