Low Power Design Techniques Research And Application Of Digital Integrated Circuit

Minimization of power consumption is the key technique in modern VLSIdesign. The increasing market of mobile product, such as PDA, mobile phone, digitalvidicon and digital camera, has stringent demand in low power and has greatlypromoted the research and development in mobile fields. In addition, power hasbecome a key concern in VLSI design. With the development of chip integration,cooling problem has become the main factor that affecting the design reliability andpackage cost. All above factors make power optimization a kernel faced in VLSIdesign.This paper investigates the application of low power techniques in VLSI designand implements the low power JPEG2000 encoder. In this paper, various low powertechniques from system level to layout level are firstly discussed. Then three lowpower techniques, including clock-gating, bus-invert and dual-voltage-scaling (DVS),are discussed and researched further. At last the VLSI architectures of the three lowpower techniques are realized. Clock-gating is the most popular low power technique.This paper mainly discussed register clock-gating technique and resolved theproblems that would probably appeared such as design for testability (DFT) problemand timing problem. For RISC processer, clock-gating can reduce power by 18.8%.Bus-invert is very effective for designs with large number of bus data exchanges. Thispaper first discussed the Markov model and switching characteristic of the model.And then bus-invert techniques and improved bus-invert techniques are contrasted byapplying them to some benchmark circuits. For RISC processor, bus-invert canreduce power by 11%. When applying bus-invert in only one bus, the average powerreduction is 1.8%. As the power consumption of CMOS integrated circuits isproportional to the square of the voltage, DVS technique becomes a most effectivelow power technique. This paper mainly discussed five key problems in DVS designand presented a novel design flow that can be easily integrated into exsting designflow. For RISC processor, DVS technique can reduce power by 28.5%.Finally, combinating the above three low power techniques, a low powerJPEG2000 encoder was fabricated in UMC 0.18um 1P6M standard CMOStechnology. 350K logic gates (standard two input nand gate) plus 550Kbits on-chipSRAM were integrated in a 4.9mm x 9.9mm die area. The core supply voltage is 1.8Vand the I/O supply voltage is 3.3V. The operating frequency in DWT is 50MHz andthe processing frequency in EBCOT is 100MHz. The power consumption achievedthrough Synopsys tool, Prime Power, is 465mW and is reduced by 54%.