Design Distribute Algorithm FIR Filter Based On FPGA

Firstly, the basic survey of digital signal process is introduced. And the development situation, the design flow, the design principle, the commonly used design method and the technical of FPGA are introduced. Then, a brief theory of FIR digital filter and several commonly used window functions are discussed.Distribute algorithm and the design process are put emphasis on. How to get FIR filter coefficients and process those coefficients are introduced. The dissertation expatiate on the distribute algorithm. The key operation in FIR digital filter is multiplication operation, and it can convert multiplication to look up table and addition by adopting the distribute algorithm. It is very suitable to adopt distribute algorithm in FPGA, because there are look-up tables in FPGA. It is thought over the problem of resource and frequency in this dissertation. It can get the result of 17bit and 14bit multiplication operation every four periods by using look-up table and the operation of shift and addition. An adder tree is designed to economize the hardware resource. The positive number and negative number process respectively and two sizable numbers arrange in the same adder in the adder tree. Then the program and the optimization process are introduced. At last, the results of synthesis by using ISE and the simulation diagram by using Modelsim are given.The result of the design indicated that the digital filter has the characteristic of high speed and high efficiency and it can meet requirement of the design. The filter can operate corresponsive 1.1G times multiplication operation and 2.2G times addition operation per second when implementing it in Xilinx Vertex2P xc2vp20 and it is so fast comparing with DSP.