The Study Of Key Techniques For High Resolution And Wide Bandwidth Σ-Δ Modulator

Sigma-Delta(∑-△)ADC is a kind of high resolution ADC which employs ∑-△ modulation and digital filtering techniques.It is composed of a modulator and a digital decimation filter. Based on oversampling and noise shaping techniques, ∑-△ modulator pushes most of the noise energy to high frequencies out of signal baseband, then, the noise energy is filtered by the subsequent decimation filter, thereby gaining high SNR.∑-△ ADC, which takes advantage of the merits of modern VLSI techniques and is less sensitive to analog circuit non-idealities than Nyquist ADC, have been applicated in high resolution requirement occasion.A modulator used in a 16bit 2.25MHz bandwidth ∑-△ ADC is researched and designed in this thesis.The resolution and conversion speed of ∑-△ ADC is determined by the performance of the modulation, so modulator plays an important role in ∑-△ ADC. This thesis discusses the theory and design technique of the modulator. Several architectures of modulator and their characteristics are studied in it. In order to meet the high resolution and high speed requirement, MASH 2-1-1 cascade architecture with multibit quantizator in everystage is adopted in the system design. The oversampling ratio and sampling frequency are 8 and 40MHz respectively.Data Weight Averaging, one of the DEM techniques, has been studied and used to reduce the influence caused by non-linearities introduced by the multibit DAC of the first stage modulator. Non-idealities produced during the manufacture process, such as finite gain, finite bandwidth and capacitor mismatch of the integrater have been analysed and modeled in Matlab environment. The requirement of circuits can be obtained by behavioral simulation.The simulation result indicates that the modulator can meet the requirement when the input signal is 2MHz.Modulator circuit mainly consists of switched capacitor integrator circuits, quantizer and clock generator. 0.5μm/5V, 2P5M,N-well, CMOS mixed-signal process of Chartered is adopted to do the circuit level design using Cadence.