Study On Wafer-level Chip Scale Package For MEMS

MEMS packaging is considered as an expensive and time-consuming process in MEMS development. Unlike other conventional packaging development, MEMS packaging design has to be finalized earlier enough in the product development. Since every MEMS device requirement is unique, the packaging is hence unique and no generic packaging solution is available. For MEMS packaging, traditional metal cap sealing is expensive, however plastic packaging needs to take the routine of wafer-level encapsulation before transfer molding for the sake of moving-parts protection and hermeticity. Therefore, wafer-level chip-scale packaging is preferable in terms of low cost, bath production and reliability.In this paper, we report a development of a new wafer-level packaging structure with through wafer vertical interconnections to meet the general requirements of MEMS packaging such as High I/O density, low cost, hermeticity and a wafer level batch process. A thinned wafer cap and Wafer-level fabrication processes such as DRIE and KOH etching, bottom-up copper filling, and Sn solder bonding were adopted. The hermeticity,the bonding strength of the structure and the resistance of the vertical interconnection are evaluated. Preliminary results show that the hermeticity can meet the requirement of the criterion of MIL-STD 883E, method 1014.9, the bonding strength is up to 8MPa, and the resistance is about 50 m(?).