Design And Implementation Of A Fixed-Point Arithmetic Unit

This paper describes a 32-bit fixed-point Arithmetic and Logic Unit (ALU). This ALU includes adder, shifter, multiplier and divider. We use carry lookahead techniques to reduce the delay of carry propagation. Based on 4-bit adder modules, we can construct 16-bit, 32-bit and 64-bit adders. Shifter should implement logic or arithmetic left shift and right shift. We design a transform algorithm. With the algorithm left shift and right shift can transform to each other, so we can use one circuit to deal with all shift operations. In the multiplier unit, we use modified Booth algorithm to reduce the number of partial products. The multiplier uses the same circuit to deal with operand with or without sign. To accumulate all partial products, we use 4-2 compressor which employs the different time delay between different input and output ports to construct Wallace tree. To achieve high frequency, we use pipeline technology to divide the multiplication process into two stages. The divider unit uses non-resorting algorithm to deal with unsigned division and transforms the signed division to unsigned one. In the development of this design, we use software simulation to validate the architecture. And as a part of the CPU, this design is described with Verilog HDL and implemented in FPGA and ASIC respectively.