Design Of RS-Decoder For QAM Demodulate IC

Reed-Solomon error correction is a very important technology which exists in today's digital communication systems. Because of its excellent error correcting ability, Reed-Solomon codes has extensive applications in storage devices, communication and broadcasting, in particular forming part of the specification for the ETSI digital cable television standard, known as DVB-C.Hardware implementations of encoders and decoders for Reed-Solomon error correction require some knowledge of the theory of Galois fields on which they are based. This paper describes the underlying mathematics and the algorithms used for encoding and decoding, with particular emphasis on the choosing of algorithms for key-equation solver (KES) block and their realization in logic circuits. After the analysis and comparison of several representative decoding algorithms, we choose a VLSI solution for our design goal which plays an important role in the FEC block of a new HDTV demodulate chip.Then, we presented all the modules of this RS(204, 188) decoder which is fully compatible with the DVB-C standard, and using time-division-multiplex(TDM) which is the main idea of several methods to optimize the architecture and minish circle scale. After optimization the circuit not only meets the performance requirement of the HDTV receiver chip but also have smaller circuit scale, complexity and lower cost. Through the whole process of Verilog-HDL coding, RTL simulation and synthesis, the proposed RS decoder has been implemented with the Chartered 0.25μm CMOS standard cell technology. The result shows that the design can be used for RS(204,188) at the speed of 6.875MHz. At the end of the paper, relative simulation and test results together with the parameter of the decoder are provided. Worked examples are provided to illustrate the processes involved.