Design Of CMOS Integrated Phase-Locked Loop Frequency Synthesizer

Frequency Synthesizer (FS) is a very important block, which is used in a wireless transceiver as a local oscillator for frequency translation and channel selection. A high speed PLL Frequency Synthesizer based on TSMC 0.18μm CMOS 1P6M technology is implemented in this dissertation.A novel phase-switching dual-modulus prescaler is employed in the design to tackle the speed bottlenecks between high-speed VCO and digital counter. An advanced multi-band negative transconductance LC oscillator is designed for stable and low phase noise output. A dead-zone free Phase Frequency Detector and a programmable charge pump are employed to reduce their nonlinearity effects. Furthermore, a simple estimating technique is deduced for off-chip passive filter based on the stability and instantaneous response of the Phase-Locked Loop.The measurement results shows that the Frequency Synthesizer can operate stable both in the bands of 722MHz～938MHz and 361MHz～469MHz and has good phase noise and reference spur suppression.