Study On The Structure Of Network On Chip

These days, the microelectronics technology is in a critical moment. Driven by the demand for high density and ultimately low cast, from the birth of transistor in 1950s, the feature size of technologies is ceaselessly shrinking and the lithographic precision is becoming better and better, well the die area is enlarged. On the design level, to further reduce the cost and enhance the performance, System-on-Chip(SoC) has gained great importance and interest. The idea of SoC is to integrate the whole system on a single chip. Traditionally only one CPU is in the bus architecture, With the development system theory, multi-CPU architecture tends to be more advantageous and attractive. In 1999, several research groups proposed a whole new idea of integrated circuit architecture, the Network on Chip(NoC). The core idea is to transplant the knowledge of network technology of computer into the design of chips such that systematically solves the problems due to bus architecture.In this paper, the description of recent advances of microelectronics is presented and the architecture of current NoC system and some advanced ideas related to NoC are studied, The physical interconnection model, crossbar and topological model and other aspects of NoC are also analyzed and summarized and NoC design based on communication is discussed.Since NoC is based on the architecture of GALS, timing is an important issue. This paper analyzes the problems of jitter and skew, their generation and gives the solution to them. The intramodule clocking, inter-module clocking and metastable problem are also discussed and summarized. Finally, a Gray code read/write pointer is realized and an asynchronous communication FIFO which uses encoder read/write pointer to differentiate the empty and full state is designed, simulation shows that metastable problem can be solved using this FIFO.