The Design Of TD-SCDMA Frequency Synthesizer

At present, TD-SCDMA(Time Division Synchronous Code Division Multiple Access) system is starting to be used for commerce. The chipsets used for TD-SCDMA are also designed and tested. While these chipsets are all be imported. So it is necessary to design domestic chipsets. A TD-SCDMA frequency synthesizer is designed in this paper, third-order interpolative Delta-Sigma fractional PLL has been adopted for the frequency synthesizer designed.The principles, structures and sub-circuits of PLL are introduced and it is analyzed and compared the advantages and disadvantages of the various circuits of sub-circuits of PLL firstly in this paper. Then, the stability, frequency/phase tracking performance and frequency/phase acquisition performance are analyzed based on the loop transfer model of charge pump PLL. The phase noise performances are also discussed based on the equivalent noise model of charge pump PLL. Then, the principle of Delta-Sigma modulator is presented, especially these two familiar modulators, the MASH modulator and interpolative modulator. Excellence and shortage of them are also compared, the stability analysis of 3-order charge-pump PLL has been deduced. The analysis flow of stability is also given. And the 3-order interpolative delta-sigma modulator is realized by just using accumulator. At last, the design method of frequency synthesizer is introduced, presenting each module's circuit and simulation results. Also the behavior level and circuit level simulation of the PLL are completed.The simulation results show that the working range of the frequency synthesizer designed in this paper is from 1.98GHz~2.06GHz, with less than 25us locking time, less than -80dBc/Hz phase noise, 12.2mW power consumed and 10Hz precision and its function completely reaches the designed good. The frequency synthesizer designed has big locking frequency range, low locking time, low phase noise, low power consumed and high precision and so on, it may offer excellent reference clock for TD-SCDMA chipsets and available technique support for domestic TD-SCDMA chipsets.