Executing Module Design And DFT Of 32-bit RISC CPU

This paper designs and implements the executing module and DFT of a 32-bit Reduced Instruction-Set Computing (RISC) CPU whose instruction set is compatible to the industrial standard ARM microprocessor.The whole design refers to the Top-Down design method and the modularization idea from global architecture design to local function implementation. This CPU adopts five_level pipeline. Above all, the structure of CPU is explored through the analysis of instruction-set. The CPU design is divided into five parts: instruction-fetching module, executing module, register-file module, system-bus module and controller module. The executing module designed by this article implements barrel shifter, arithmetic and logic unit(ALU) and 32-bit multiplier and supports all the logical and arithmetic operations of ARM instruction set. Through the comparison of two different methods, the barrel shifter is implemented with full-decoded method which is faster than part-decoded method. ALU is designed on the resource-sharing basis to reduce area. 32-bit multiplier adopts modified radix-4 booth coding to reduce the number of part products, simplifys the sign extending circuit of part product by the mathematical preprocessing. To accumulate all the part products, the Wallace tree is constructed with 4-2 compressor.DFT is the design method to easy the test(manufacture test) by consciously adding additional circuits in the design. Based on the research of primary DFT method and the structure characteristic of designed CPU, the article combines the boundary scan and Build-In Self-Test based on BILBO to test. Based on BILBO BIST reduces the test area consuming by combining the scan test and BIST. For pipelined CPU, self-test and normal function can be achieved by controlling the BILBO unit altered from the pipeline registers. The designed circuit of boundary scan totally compliant with standard IEEE 1149.1 is extended to integrate BIST circuit into the test system and simplifys the process of testing.