RTL Power Analysis And Optimization With Function Simulation

The dynamic power of CMOS circuit is responsible for 70%~90% of the total power. Reducing circuit nodes' useless toggle has the great effect on saving the dynamic power by using the low power optimization techniques. The current RTL low power optimization is still depended on the designers' experiences and is applied mechanically. This paper presents a RTL low power optimization method based on the typical functional simulation, RTL code parse and expandable optimization technology library. Two tools are provided to realize the method. The tool Verilog_lp programmed with Verilog PLI(programming language interface) works to generate the circuit node toggle messages. The tool optRTL.pl programmed with Perl(practical extraction and reporting language) works to optimize the RTL source code. The tool optRTL.pl parses the RTL source code and generates the logic tree of the expression. The circuit structures which are fit for the operation isolation, precomputing and logic reorganization techniques are found out too. According to the circuit node toggle messages, the optimization guidance messages are generated by the tool optRTL.pl. An VLSI design/optimization flow based on our low power optimization method is provided and the experimental results are summarized and analyzed. The most optimization candidates which are unfit for circuit's current work condition can be filtered. The designer can determine the last candidates through the optimization guidance. Experimental results with power reductions of up to 17%～30% and even to 60% in some special work condition demonstrate the effectiveness of the method. The results indicate that the low power optimization may deteriorate the speed and area too. A tradeoff must be made between the speed, area and the power. Experience has proved the effect of the software tools to guide the designer to write the RTL code with the low power character.