Research And Design Of AES Encryption Soft IP Core

AES (Advanced Encryption Standards) was published by NIST (National Institute of Standards and Technology) in 2001, which encrypt the datas in the field of information security. There are software and hardware implementation approaches for the AES algorithm. Compared to sofware implementation, hardware implementations provide more physical security as well as higher speed. Many works have been done focus on the optimization of S-Box, MixColumn and KeyExpansion module.In this thesis, a complete RTL implementation of AES encryption IP core is presented. At the beginning of system structure, C++ is used in the behavior level of AES and Finite State Machine of AES IP core is designed to understand clearly the relationship of logic and timing between the modules. Based on these works, we define the I/O ports and its timing relationship of the AES encryption IP core. In the process of system structure, based on inter-round and intra-round pipeline architecture, we present an efficient hardware design to increase throughput for the AES IP core. During the modules design, the implementation of S-Box is optimized to avoid too many ROM used by using composite field arithmetic and 5 pipeline level. To work with these modules, the architecture of 7 pipeline level has been used in the KeyExpansion module design.Finally, we finish the design of AES soft IP core. Function verification and timing analysis prove the design of RTL codes is feasible. Testing in FPGA, the clock frequent of our design can reach 100MHz-200MHz. AES soft IP core can perform encryption at a clock frequency of 180MHz achieving a throughput of 23.04Gbps.