Research On Hardware Implementation Of Algorithm For AES

WLAN with its flexible movement, low cost and powerful expansibility is widely used. However, going with its facility, the security leak has become the severe problem. The security problem remained only the obstacle when the WLAN was to enter the area of information industry. To solve this problem, together with the Nios soft core embedded processor design contest 2005, this paper was given the subject'Secure Access Point Based On The Hybrid Pipelining Implementation of AES in the Feedback Mode'based on the theory of hybrid pipelining implementation of AES in the Feedback Mode.NiosⅡ/f core and Altera's CycloneII series FPGA was chosen in this application. Lan91c111 chip was used as ieee802.3 physical layer. Series chips of Intersil Co.Ltd were used as ieee802.11 physical layer. There is a piece of circuit schematic of this application in this thesis. This scheme had passed first trial and had got through to the finals. Because of some difficulties, the ieee802.3 part was replaced by USB2.0, ieee802.11 part was replaced by ptr4000 wireless transceiver model. After the changes, whether the AES algorithm is right or wrong can be easily verified on chips.The AES algorithm is a kind of symmetric block cipher. It supports key size of 128 bits. The data block is also 128 bits. The number of rounds (Nr) is a function of the block. Every round needs a derivation of round keys that have key length of 128 bits as the block cipher. So key expansion is need before encryption. This paper focuses on the theory, process, timing simulation and the result of key expansion. The whole algorithm is consisted of this part and the AES algorithm core model. At last, by using 56-pins CY7C68013-56 FX2 series USB chip of Cypress Co.Ltd, this article shows the method of the firmware design and the application that is used to input the plain text.