A Research About System-On-Chip's(SOC) Design For Test

Nowadays the development of integrated circuit still abide by the famous Moore Law. While the scale of the VLSI is getting bigger and bigger and the complexity of the SOC which is based on the integrated IP is even higher, the traditional functional test can't cover the most of the fault of the chip and it is time consuming. As the manufacture of the chip is developing too fast, especially when it comes to the deep sub-micron, the physical defect in manufacture is growing fast which has become the most concern of the IC designer. The cost of test is getting higher and higher and it takes more than a half of the cost of the design. In the face of all kinds of challenge it brings, design for test has become the indispensable step of the IC design flow. Design for test is to think about the test at the right beginning of theproject and comes along the design flow, add some test logic to the design that solve the test problem and make it testable, so that lower the cost of the test. DFT verifies that the design does not have manufacture defect by focusing on the structure rather than the functional behavior. The scan design which is based on the stuck-at fault model is the prevalent method of DFT. But for SOC, the design is based on the reusable IP which would bring in some test problems. So, we have to introduce some other method of test besides scan test, such as memory BIST, boundary scan and embedded core's functional test.The main idea of this dissertation is to adopt the divide-and-conquer method for the PAV SOC design. That means to break down the design in some parts and finish the DFT separately such as the scan design of the user define logic, the BIST of the embedded memory, the test of the embedded core and boundary scan. The test of the embedded core is provided by the IP provider, the JTAG can be finished abide by the IEEE1149.1, the memory BIST is added in the RTL stage and synthesized with the other logic. This dissertation is focus on the scan design with the existence of multiple IP. It has to accord with more strict DFT rules with the existence of multiple IP.The main result of this dissertation is to do the testability analysis and measurement for SOC design which is containing nearly 2 million gates and solve the testability problems, to adopt the full scan methodology to add the scan design in the chip level of the SOC and add multiple scan chains as well as test logic, to automatically generate test patterns for the chip based on the exist scan logic then compressthe test patterns to reduce the test time. Especially, this dissertationcompares the SOC design with a similar scan design of a DSP to makea conclusion of the main problem affecting the result and how to get ahigh fault coverage scan design. The modification of the problem offault coverage is to consider the test requirement thoroughly at thebeginning of the design and accord with the strict DFT rules.