Design For The Decimator Of Second Order Sigma-delta ADC

The sigma-delta analog to digital converter (ADC) is a IC product that is explored by Beijing MXH Device Co.,Ltd. Using top-down way, the design is finished with CSMC 0.5um two metal craft.This paper, "A Design for the Decimator of Second Order Sigma-delta ADC", is a part of sigma-delta analog to digital converter including writing the behavior code with Verilog for the decimator, simulating code, simulating the theory of schematic, drawing layout. The decimator with good ability of filtering the noise is used in sigma-delta converter. Decimate the analog signals using decimation which is quantized. The total circuit with differential input is supplied by 3.3 voltage. The input signal root in the out of modulator. The digit of input signals is 1 bit, and the digit of out signals must be 13 bits. K is the decimation ratio which equals 16. The total circuit consists of more than three thousand components.The main performance of circuit, including coder circuits, full adder circuit, clock divide circuit, integrator circuit, differentiator circuit is analyzed in implementing main function block of the schematic after referring to plenty of bibliographies and analyzing the theory of schematic. Through considering the correctness of the whole circuit, write the Verilog code of the decimator, finishing the simulation of code validation through the software of Modelsim. Accomplishing the simulation of the whole circuit through the software of Hspice. The two results of simulation for the two circuits are completely consistent. At last, layout is finished. Both LVS and DRC for layout are passed.