Design And Realization Of The X-Stream Processor Host Interface

With the expanding area of compute application, stream media and scientific computing is becoming an important kind of application of processor. Stream architecture which aims at media processing and scientific computing is a new high performance architecture. X processor is an implementation of this architecture.This paper selects the stream architecture as the goal of research, and aims to design and implement the host interface of the X-stream processor. In the communication between the stream processor and the host, the stream instruction and data are packaged in the form of message packets, and the packets are scheduled to the stream processor by the host interface, so the stream can flow between the host and the stream processor.The design of the X-Stream processor host interface mainly includes module partition, logic design, simulation and verification. This paper discusses the communication protocol of the host interface and the design of communication components, realizes the design and verification of all components, and presents the method and process to test the design.The host interface of the X-stream processor is described in Verilog hardware language. The simulation and verification test of the design is completed in the NC-Verilog by the down-top methodology. The design has passed standard and random test vectors of high coverage rate and actual testing procedures. These solution ensures the correctness of the design and the completeness of the verification.