The Full-Custom Design & Optimization Of Multiplication Component Of YHFT DSP

Digital Signal Processor (DSP) is a processor with paticular architecuture and is the core of digital signal processing systems.YHFT-D4, designed by YHFT-DSP Lab, is a 32-bit high performance Digital Signal Processor.The processor with VLIW architecuture can issue 8 instructions per cycle.At the frequency of 250MHz, it can finish 2000 million operations and 2000 million 8-bit MACs in a second. The performance of multiplication is an important criterion of evaluating the performance of DSP.In this paper we had designed and implemented the multiplication components of YHFT-D4.Two seperately multiplication components which be made in YHFT-D4 have been implemented through pipelining of two stages.All sorts of new technologies were used in design of the multiplier, such as using Finite-Sign-Extend technology and improved Booth-encode technology to reduce the amount of partitial product, using rapid and regular structure of 4-2 tree.At the same time, the SMD technology be designed in the pipelining of the multiplier. The structure of Han-Carlson adder which speed,area and complexity have been taken into account had been used in the second stage which sums the last results.In this paper,some new and improved structure format were introduced in designing circuits; the method of building-model were introduced in customizing the size of transistors,and the performance be more optimized;In layout designing,to reach the purpose of regular and reliability of layout, introducing the method of modularizing plan; At last, after the multiplier had been designed and typeout,we designed a set of testing method and the result of testing is wonderful, so the result not only proved immediately the advantage of full-custom design but also proved indirectly the correctness ,practicality and simplicity of the new test method.Using the DC tools of Synopsys' Co, under typical condition 0.18um CMOS technics lib, simulate and analyze.The delay of critical path of the multiplier is 4.2ns, about 240MHz. However, Using full-custom design method, under the same conditions, The delay of critical path (logical delay) is 1.88ns (Hspice), about 500MHz. Received a very large improvement in performance.