Research And Implementation Of Low-power Test Structure Based On Segment Transformation

Due to the growth of the complexity of digital integrated circuit, especially the appearance of system-on-a-chip, testing faces more and more challenge. During the process of IC testing, the power dissipation is much higher than that of normal operation. There are two reasons for this phenomenon. One is the correlations between vectors are small. The other is testing needs switching nodes as many as possible. The power dissipation could damage the IC during the process of testing. Therefore, reducing power consumption has become an important target in testing technology and power dissipation has profound influence on design for testability.In this paper, firstly the function and basic principle of digital circuit testing technology is introduced, the cause of circuit test power is analyzed and several methods to reduce test power in present design for testability is enumerated.Secondly, based on the analysis of the process of test pattern generation during BIST process, the problem caused by LFSR as test generator is pointed out. In order to solve the problem, a low-power BIST strategy based on segment transformation on the basis of analyzing distributing rules of effective test vectors is proposed. By using fault simulator to eliminate useless test vectors that make no contribution to increase fault coverage, the remained effective test segments are delivered to CUT according to the principle of lowest test power.On the basis of this strategy, the structure of low-power BIST based on segment transformation is realized. By describing the functions of every component part, the two stages of BIST running process: generating effective segments and transformation between these segments is introduced in detail. The experimental results show that this low-power BIST structure can avoid lots of useless test vectors to run on, reduce test power and lessen test time.Finally, directing at the problem that parts of primary inputs can't be feedback by the circuit nodes of CUT, a test generation algorithm based on feedback of exclusive-OR gate is proposed. By adding a shift register, this algorithm could increase the probability of successful finding and reduce hardware expense. Experimental results show that the algorithm can be an effective complementarity of self-feedback test.