The Research On Fault Model And Fault Collapsing Of Digital Circuit

With the rapid development of integrated circuit design and manufacture techniques, great complexity and larger scale of integrated circuit make test more and more difficult. Traditional test generation methods can hardly meet test requirements because of long test generation process, high test complexity and low fault coverage rate. Some methods have been employed to resolve the problem. In sum, the research of fault collapsing, new fault model and test generation have been hotspots in digital circuits testing field.The main works of the thesis are showed as follow:(1) Background of test techniques, fault simulation and ATPG algorithm are explained, and introduce the techniques of design for test.(2) The methods of equivalent fault collapsing and dominated fault collapsing are analysed from structure and function. Faults on fan-out line are researched to give the dominated relation between faults, which can further collapse faults of target fault sets.(3) Concurrent test generation method is further researched based on analysis of the principle of multiple faults model. Multiple faults model is used to seek concurrent fault sets with common test patterns for target fault sets after equivalent fault collapsing and dominated fault collapsing. Based on concurrent relation, the fault sets are partitioned into different groups with grouping algorithm, which generates the concurrent test sets. Experimental results show that concurrent test pattern generation method will generate reduced test pattern sets compared to the traditional methods.