Implementation And Research Of MAC Sublayer For Network Processor

With the increase of protocols and services for broadband networks, Network processor (NP) has become the core of switcher and router. The architecture of NP is generally composed of multicore. And NP commonly uses the ASIP technology. NP has the advantages of high performance and flexibility. The MAC element which exchanges the data between NP and physical layer is the important interface for NP. The performance of the MAC sublayer impacts the I/O performance of network processor greatly. This dissertation researches the design and implementation of Ethernet MAC sublayer, which is incorporated with the project of network processor. In this paper, a MAC element which has standard bus interface and 10Mpbs/100Mbps data transfer rate has been designed on RTL level.This dissertation studies the protocol of the MAC sublayer for IEEE 802.3 standard and then describes different MAC frames' structures. To introduce four components of the Wishbone interconnection architecture, classic bus cycles and interface signals.This dissertation detailedly studies the architectures of the MAC element. its architecture is composed of receiver module, transmit module, MAC control module, register module, buffer module, Wishbone interface and MII interface module. The MAC element can transmits data with Wishbone interface through FIFO. It detailedly describes the designs and functions of the receiver module, transmit module, buffer module and Wishbone interface. It has completed the function simulation and verification of this design. The verification results show that the design meets the requirement of the MAC sublayer.The contributions of this dissertation are as follows. A MAC element with Wishbone interface which has generality is proposed. The way for parallel CRC algorithm is detailedly presented. The architectures of the MAC element are detailedly designed on RTL level and implemented by Verilog codes.