The Implementation And Optimization Of H.264 Decoder For Video Of D1

The H.264 video compression standard has achieved a significant improvement over all previous video compression standards. In terms of coding efficiency, the new standard can provide at least 2x compression improvement over the best previous standards and substantial perceptual quality improvements over both MPEG-2 and MPEG-4. At the same time, the H.264 standard is significantly more complex than any of the previous standards. Consequently, the H.264 decoder is expected to be significantly more demanding in terms of computations and memory requirements. Since any decoder should be able to handle all "legal" bit streams (i.e. worst-case scenario), the implementation of the decoder is even more complicated. Moreover, the development of an embedded decoder implementation where the internal memory size is limited is a challenge.The TMS320 DM642 Digital Media Processor (DM642) is the highest-performance fixed-point DSP from Texas Instruments. The DSP core processor has 64 general purpose 32-bit registers and eight highly independent functional units - two multipliers and six arithmetic logic units with VelociTI.2 extensions. The VelociTI.2 extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI architecture. The DM642 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. In a word, With the processor's 600MHz processing power in production today and an aggressive process technology roadmap for continued higher clock rates, this DSP is most suited to overcome the complexity and computational requirements of H.264. To develop and optimize H.264 decoder software on the Texas Instruments' TMS320DM642 Digital Media Processor is the main task of this thesis.In the first part of this thesis, the H.264 video compression standard is introduced, following with its extension - FRExt. Besides, the application of H.264 video compression standard is also discussed.In the second part of this thesis, the architecture and complexity of H.264 software decoder are analyzed, and the emphasis and difficulties of optimization are figured out. The efficiency of the decoder based on PC is listed out afterwards.In the third part of this thesis, the system of H.264 decoder on TMS320 DM642 Digital Media Processor is introduced. This system contains three parts: the decoder software which is migrated from PC software with several changes; the network part and video out part which are developed to ensure the integrity of the system. The DSP/BIOS is the base of the whole system, and its principle is introduced along with the implementation of the system. Combing with the characteristics of TMS320 DM642, the method used to optimize H.264 decoder is figured out. At last, the efficiency of the decoder based on DSP is list out.The experiments results prove that the H.264 decoder based on DSP in this thesis is integral and effective.