Polygon Matching And Comparison Analysis In OPC

When the process of VLSI has developed to VDSM (Very Deep Sub Micron), the complexity of VLSI is largely increased and the feature size has become smaller. When the feature sizes in the design are near or shorter than the wavelength of the lithographic light source, the real shapes created on wafer will not be consistent with the layout. In this case, Optical Proximity Effect (OPE) happens. To solve the problem of OPE, Resolution Enhancement Technology (RET) emerges to retain the conventional IC manufacture equipments to create circuit with smaller features. Among the Resolution Enhancement Technologies, Optical Proximity Correction (OPC) has become the most important technique.OPC is not a one-pass-through but an iterative process. Post-OPC verification and fixing is an essential part of the OPC technique. However, the traditional way of post-OPC fixing is redoing OPC for the whole layout once again. The method not only wastes the result of the previous OPC and increases the computation complexity, but may also introduce some new errors. For this reason, a regional correction method is found. We call it Smooth OPC Fixing technique. It utilizes the previous OPC result and fixes the error within its area. In this way the efficiency is highly improved.This paper analyzes the polygons in the layout, the smallest cell in a layout and attempts to discover the optimization method for OPC. It presents a liner polygon matching and comparison algorithm for post-OPC fixing technique. By comparing the pre-OPC and post-OPC layout, it recognizes and records the fragmentation and offset information. Therefore the post-OPC fixing process can reuse the previous OPC result. By avoiding redoing OPC all-over again, the entire processing efficiency is highly improved.