Research Of A BIST Scheme Using Test Patterns Applied By Circuit-under-Test Itself

The cost for testing the modern Integrated Circuit (IC) is usually very high. This is because of the complexity of ICs themselves and less attention paid by the designers who are usually interested in IC's functions. So, the test of IC is, generally speaking, very difficult and needs very expensive testers and long test application time. A good method to address this problem is Design-for-Testability (DFT). The fundamental idea of DFT is to consider the test issue while designing, in order to make the ICs to be tested easily. Build-In Self-Test (BIST) is a kind of most important and widely used DFT technologies.A proper Test Patten Generator (TPG) is the essential part in any BIST scheme. There are two typical TPGs. One is the pseudo-random TPG based on the Linear Feedback Shift Register (LFSR) and the other is memory TPG based on the Read Only Memory (ROM). These two methods have their own advantages and disadvantages; therefore, they are often combined to meet a balance between the performance and the cost.On the basis of introducing the principle of digital circuit testing and the common strategy of DFT, we propose a BIST scheme using test patterns applied by Circuit-under-Test (referred to as TPAC) itself for combination circuits or full-scanned sequential circuits. In this approach, CUTs are no longer only regarded as test objects, but also a sort of available resources. By feedback connecting some of the interior nodes to the primary inputs, TPAC can generate and apply the next input vector by CUT itself, so as to improve the performance of the BIST. The test generation method using"feedback strategy"is the main difference between TPAC and the other BIST approaches.In this paper, we expound the basic idea of TPAC, and the similarities and differences between traditional BISTs and TPAC in the various stages of test procedure including test pattern generation, test application and response analysis. In additional, we propose three TPAC strategies: Entire-Feedback, Group-Entire-Feedback and General- Feedback for various CUTs and their test set. Furthermore, a mathematical description for TPAC is presented. The experimental results on the ISCAS85 circuits and MinTest test set demonstrate that the proposed scheme not only can achieve almost 100% single stuck-at fault coverage, but also has an average 54% decrease in test data volume compared with LFSR reseeding approaches.Our current works are very infantile and it is just a beginning of TPAC researching. We believed that this method will have a wide research foreground because of its low area overhead and short test length (that is less test application time).