Design Of APB Bridge Based On AMBA Architecture

With the rapid development of technology in deep submicron,the scale of integrated circuit(IC)grows increasingly.It has not been the day when digital integrated circuit been designed based on timing-driving,but the time when intellectual property(IP)reuse been taken popularly.This design method is widely applied in the system on chip(SoC)field either.The on chip bus design is most cared in IP-reused based SoC design.Thus,several bus standards were proposed.Among those standards, the advanced microcontroller bus architecture(AMBA)is the most favored.It has been the popular industry standard.The AMBA2.0 defined three class of bus,including advanced high performance bus(AHB),advanced system bus(ASB)and advanced peripheral bus(APB).The APB Bridge is one part of APB.It is between AHB and APB bus,as a critical part to connect AHB and other peripherals.This dissertation is based on the GS32S CPU of Godson-1 as the AHB master.A method to design the APB Bridge is proposed,and doses some research from 3 parts as follows:First,the different on-chip bus standards are compared.Research on the AMBA2.0 is done deeply,and the advantage of the standard is analyzed.A concrete method to design the APB Bridge is put forward,which can meet Sequential, Nonsequential,and Back-to-Back transfer mode.Second,after the comparison and analysis on VHDL(Very-High-Speed Integrated Circuit Hardware Description Language)and Verilog HDL,the latter is choused for its advantage at description the gate-level switching circuit.Third,the testbench with Verilog HDL was written for the designed module,and the timing simulation was complied in ModelSim developing system.The download file was configured for in the QuartusⅡdeveloping system.The module passed the hardware test,realized design request.The research achievement has accomplished the conversion from AHB to APB, realized the coordination between lower peripherals and higher CPU.It has higher applied value in development,application and further research of embedded SoC.