The Design Of A Full-duplex Transceiver Chip

With the development of the distribution system in automation field, the RS-485 bus standard which supports multidrop and long distance communication becomes popular. This standard has many advantages,such as flexible hardware design,convenient control and low cost, and it can be used for all kinds of charge system and field supervise system. So it's worth to design a full-duplex tranceiver chip.In this paper, a low power RS-485 BUS full duplex transceiver chip has been developed. Design of each block is described in detail, layout consideration is also presented in brief. The chip also has the following features: standby current of 1nA, maxim data transmission rate of 250 kbps, maxim loads number of 32. The chip has internal short circuit protection,open circuit protection,lightning strike protection and thermal shutdown protection circuit. As the chip is widely used in long distance data communication, the application environment may present a number of serious problems even destroy the whole circuit without those internal protection circuit.The 0. 8μm High Voltage CMOS process is used to fabricate this chip. We use Cadence Spectre to run simulation, and results of system simulation indicate that the performance of this circuit meets exactly with the design goals. Meanwhile, we use Cadence Virtuoso to edit layout. The chip has been taped out, and is under testing right now.