| The wideband speech coder standard G.729.1 is suggested by ITU-T in 2006. Based on the condition of network, the bit-stream, which is transmitted by the G.729.1 encoder, may be variable.With the development of technology, more and more application about G.729.1 will be achievable.The characterized task of this paper is the IP core design for G.729.1 coder worked on FPGA platform. Therefor, more research and experiment has been carried out about embedded system with IP soft-core design. And a real-time G.729.1 coder has been come ture in a hardware project firstly. On the other hand, more work will be putted into practice in favor of the experience from IP core design of this paper.The valuable research fruits in this paper follow as:1. Analysis about the arithmetic framework and parameter of G.729.1 protocol is valuable, which is required in embedded system design. In order to collect and optimize test vector for embedded system research, a test application about G.7291 has been achieved on PC platform.2. According to the theory about IP core design in Reuse Methodology, the paper discusses the G.729.1 codec embedded system design based on NiosII CPU.3. The paper describes the real-time G.729.1 decoder firstly realized on FPGA platform. In this case, the IP core modules of arithmetic accelerating which is designed for G.729.1 coder are needed.4. It is summarized some superiorities on Modern DSP Techniques, which is compared with Tradition DSP Techniques. In addition, the conclusions will be the guidance of correlative wideband speech coder design. |