A Novel Intergrated Circuit Cu Interconnect Process Research

With the increasing integrated density and decreasing critical dimension of integrated circuit, interconnect delay is one of main factors which influence chip speed. Compared with delay of local interconnect, delay of globe interconnect is in a decisive place of controlling chip speed. Different kinds of methods for decreasing interconnect delay are hot focused by researchers and methods are mainly from process or design aspect.Mainly for globe interconnect, a novel air-gap copper interconnects process has been studied in this thesis from process aspect. Referencing from MEMS designing method, free standing copper beams were manufactured by using plating, CMP, sacrificial layer process. CMP process was studied with copper beams structures and Al2O3 sacrificial layer, and results satisfied requirement of lithography and wet etching. With 3~4um thickness sacrificial layer, CMP time is almost 30 minutes. Al2O3 sacrificial layer was studied by wet etching. Free standing copper beams were prepared after removing Al2O3 sacrificial layer by wet-etching.A new test structure was used to evaluate the influence of low k dielectric to interconnect capacitance, by measuring interconnect capacitance of air, FOX15,PI and SiO2 dielectric. As a result, interconnect capacitance could be greatly decreased using air dielectric. Compared with SiO2 dielectric, interconnect capacitances of air dielectric and FOX15 dielectric are decreased 53.4% and 23.5% respectively. Simulating result and measuring result matched well by ANSYS finite software. Using this simulating model, intra-level interconnect capacitances are much smaller than inter metal interconnect capacitances with increasing ration of inter metal interconnect length to intra level interconnect length. TaN diffusion barrier layer was deposited by reactive RF sputtering under different nitrogen pressure. With nitrogen pressure 10%, annealing at 200-600,resistivity changed little.This new process provides an opportunity for reduction of the delay due to conductor lines. Chip speed will be greatly improved by integrated this method into IC process.