Research And Application Of QC-LDPC Encoding And Decoding Algorithms Used In DTMB Standard

LDPC code(Low-Density Parity-Check Code)is a powerful error correcting technique that is a good code near Shannon limit performance,invented by Gallager nearly 40 years ago.Thanks to its excellent performance and its bright application prospect such as optic communications,satellite communications,deep space communication,the fourth generation mobile communication system,digital subscriber loop with high speed or hypervelocity,optical and magnetic recording system, LDPC code is widely considered as next-generation error-correcting code for telecommunication and magnetic storage,which is put a high premium on by academic circle and IT circle.And LDPC code has been the most spectacular spot in error-correcting coding area.It's clear that LDPC code will displace Turbo code in the near future.The academic significance and commercial value of study on LDPC,also the impulse on associated technology in IT area are great.Channel coding adopts LDPC as its inner code and BCH as its outer code in DTMB (digital terrestrial media broadcasting) .The decoding algorithm and hardware implementation of QC-LDPC in DTMB are the focus of this thesis.In this paper,the basis of communication and channel coding theory is introduced briefly.After the definition of LDPC code,the encoding and decoding algorithms,also the performance analysis of decoding algorithms are studied., Based on the probability domain and the log likelihood ratio domain of BP decoding algorithms are paid more attention to, including the BP-Based,normalized BP-Based,Offset BP-Based algorithms,and presents a new algorithm based on BP algorithm according to the regularity of DTMB coding matrix. The new algorithm uses Serial Schedule Message Passing and reduces the complexity of the Check-Node Update operation, not only improve convergence property but also reduces the decoding complexity. This paper simulates the performance of different algorithm of LDPC codes in DTMB, simulation results show that the new algorithm performs less than 0.1dB worse than BP algorithm at the BER=3×10^-6, and its average iteration number can be reduced to 50%, not only improves convergence property but also reduces the decoding complexity. Then it mainly discusses the hardware design of the LDPC decoder.Including full parallel architecture, partly parallel and serial architecture has been analyzed, partly parallel architecture has been choosed in the design. The design is achieved in the FPGA chip Virtex5 XC5VLX220 of Xilinx and also be verified by the logic analyzer. The design is described in Verilog.By performing maximum 10 decoding iterations, the decoder can achieve a maximum bit throughput of 44Mbps.At last, it points out the existing shortage and the direction for further research.