Design A 10-bit SAR A/D Converter Based On CMOS Technology

With the continuous development of application field for wireless communication, portable consumer electronics and automotive electronics, high-performance, low-power, low-cost SOC become main trend of integrated circuit design. The development of SOC requires A/D converter, other analog circuits and DSP to be integrated in a chip. The purpose of this thesis is to design a medium-solution, low-power, small-size SAR A/D converter to meet the development needs of SOC.In this thesis, module circuits design of a 10-bit resolution, low-power, small-size SAR A/D converter based on CMOS technology is presented. To cancel offset voltage, a preamplifier-latch comparator using self-calibration technique is adopted. Simulated by Cadence, the comparator can achieve 85-dB gain, 0.28-mV sensitivity and 0.14-mV power consumption. All the simulation results meet the performance requirement of high-speed, high-solution and low-power. Design a modified charge-redistribution DAC by combining 6-bit MSBs'binary weighted capacitor array and 4-bit LSBs'resistor array. The DAC can lower nonlinear error and the requirement of capacitors'matching. Simulation reveals the DAC achieves high speed and linearity. Influence of DAC's nonlinearity due to capacitor and resistor's mismatch is discussed. Principles on how to improve the performance of DAC is also considered. Finally, based on consideration of mix signal IC layout design, the layout of ADC is given. The core area is 957μm×849μm.