Research And Implementation Of Digital Front End Technology In Software Defined Radio Application

Along with the rapid development and the expansion of communication technology,many problems including the existence of different communication architecture,the compition between various standards and the usage of frequency resources become more and more urgent.Software Defined Radio(SDR)provides the modem solution for above problems.The SDR can offer updated functionalities and improve the communication services which are transparent to the customers.The design technique of the Digital Front End(DFE)part in SDR is critical,as which is able to influence the distance between the digital part and the antenna.Based on anterior theories and research results,this thesis made some improvements to the algorithm of DFE part which enhances the system performance and makes it more fit for the SDR application.The critical problem of the DFE is the Digital Signal Processing(DSP)bottleneck, it is hard to use an inexpensive general DSP processor to finish the rough task,which is to blame for the low MIPS performance.With respect to a SDR DFE receiver,the downlink path consists of mixer,filter,multirate processing and etc,which are the most resource consuming and intense computing part of the design.General DSP processor can not afford such high volume data throughput.Instead,all the designs in this thesis are based on Field Programmable Gate Array(FPGA)technology,which is born with parallel pipelining feature and other utilities.An integrated DFE downlink design is implemented.With respect to the conventional design flow of the FPGA based applications, there is always a gap between the design of the algorithm and the implementing of the corresponding fixed point design.This gap might blind the system designer and conceal some glitches or bottlenecks inside the system.After the algorithm is ready, the mathematic description should be converted to the Hardware Discription Language(HDL)first and then the consumption of the resources and the implementing performance can be accessible after the hardware simulation.In this thesis,MATLAB SIMULINK environment is employed to finish the algorithm and system modeling,with the help of powerful toolboxes and hardware mapped simulink blocks,immediate floating and fixed point results can be evaluated at the system and algorithm level,the corresponding codes can be generated and implemented to the real hardware thanks to the System generator and ISE development tools.Moreover, on chip block status can be read from the embedded logical analyzer and the hardware results could be evaluated on the desktop.In sum,in this thesis,improvements have been made to enhance the CORDIC algorithm and provide a better performance NCO in DFE,which has been implemented in FPGA hardware.After that,the low cost multirate fiters have been discussed and corresponding modeling and implementing are also proposed.Besides, an integrated DFE processor which consists of improved NCO,multirate filters and gain controller is designed,simulated and implemented.Moreover,all the designs should thanks to the advanced EDA based design flow.Finally,a conclusion and future view of the related work have been made at the end of the thesis.