Development Of Error Detection And Correction EMC IP Core

Nowadays, memory controller is a very important part to access memory in most computer systems. But when memory controller accesses the external memory, some errors may occur owing to memory itself or high-octane particle from space. These errors would affect not only the performance of the computer system but also the transmission of the key data. So it is necessary and valuable to design an external memory controller (EMC) which has error detection and correction function.This paper made a deep research of the relative technology of memory, error detection and correction and memory controller. Firstly, the architecture, address, data storage and timing control of some types of memory were discussed, which are used abroad in high-performance system and mainly include Asynchronies SRAM and some types of dynamic memory. Then some error detection and correction methods are discussed especially optimal odd weight hamming code. Finally the architecture and technology of memory controller that we adopted is analyzed. Then two EDAC, which according to the time specification of EMC, were designed to protect 32bits SRAM and SDRAM. The EDAC for SRAM can execute 32bits, 16bits and 8bits operation and the EDAC for SDRAM can carry out 32bits operation. Based on this, a new architecture of external memory controller with EDAC was presented. And memory controller IP core with EDAC was implemented with verilog hardware description language, the simulation and logical synthesis of which were done either.