The Design Of A 16-bit Sigma-Delta Audio ADC

Both important theoretical and experimental progress has been made in the digital signal processing (DSP) technology in the past a few decades. DSP is gradually replacing the traditional analog signal processing (ASP) in various areas due to its high reliability, strong flexibility and low cost. However, ASP and the analog integrated circuit design have not phased out of the stage. Instead, they are playing an unreplaceable role in many cases. Undoubtedly, the essence of current high-speed digital circuit designs is still the analog ones. As the kernel of DSP, the analog-to-digital converter (ADC) has various architectures.Among them, pipelined and oversampled Sigma-Delta ADCs are most widely adopted. Pipelined ADCs are capable of achieving high conversion rates, but their high sensitivity to the component mismatch increases the circuit complexity. The power consumption becomes very large beyond the 14-bit resolution. On the other hand, by combining the oversampling with the noise shaping techniques, Sigma-Delta ADCs exhibit high precision, but are hard to process high-frequency analog signals. Notwithstanding, since a lot of work can be left to a digital filter after the front-end Sigma-Delta modulator converts the analog input signal to high-speed bit-streams, Sigma-Delta ADCs are easy to be integrated in the very large scale, leading to relatively lower cost. The Sigma-Delta modulator is essentially a feedback structure, immuning of many non-ideal effects of analog circuits. Compared to Nyquist sampling, the oversampling technique makes the design of the front anti-aliasing filter relatively easier. These advantages of Sigma-Delta ADCs have extended their application fields.In this work, we investigated the structure and circuits of the modulator in a high resolution ADC used in the audio signal range with a 20 kHz baseband frequency and a 16-bit resolution. Principles of the Sigma-Delta modulator were first discussed, as well as the effects of different structures and parameters on the resolution. The Sigma-Delta modulator with a second-order single-loop structure was then designed. Noise models of the Sigma-Delta modulator were constructed under Simulink with major non-idealities taken into account for behavorial simulations. The validity of noise models was verified. After considering the non-idealities, the as-designed Sigma-Delta modulator exhibits a 95.6 dB SNDR and a 15.58-bit ENOB under the 12 MHz oversampling clock and 256 oversampling rate, satisfying the resolution requirement. Circuit blocks such as the gain-boosted cascode amplifier, switched-capacitor integrator, quantizer and two-phase non-overlapping clock signal of the modulator have been implemented based on the behavioral design. Hspice and Spectre were finally used to simulate these circuits.A 0.35μm mixed CMOS process is used in the design. The threshold voltage of NMOS and PMOS is 0.67 V and -0.78 V, respectively. The power supply is 5 V. The Nyquist convertion rate is 40 kHz, and the oversampling rate is 256. The obtained modulater has an SNR of 85 dB, a convertion resolution of 14 bits and a power consumption of 17.12 mW, suitable for high-fidelity digital-audio applications.