Design Of A I~2C-bus Real-time Clock Chip With SRAM

Consumptive electronic devices play avery important role in the broad electronical industry. Real-time Clock counts seconds, minutes, hours, date of the month, day of the week,month and year with leap-year compensation. It has been widely used in industrialelectronics and consumer electronics. I~2C bus protocol is a serial bus protocol which is brought forward by Philips semiconductors company. The protocal brought convenience to many designer engaged in designing some systems based on MCU,ASIC,CISC,it has many advantages in data transferring rate and system stability. Many chips can be connected by only two wires.In this thesis a clock chip used in consumptive industrial control field and electronic devices was designed.The chip integrated a 240 bytes SRAM for important data storaged. For broad applications,the interface circuit of our chip use I~2C bus as our interface standard. The data transmission rate is up to 100kbps.At first, this thesis introduces the pin description and block diagram. The interface circuitry is designed to meet the requirements of I~2C protocol.A 100Hz special divider is designed for the counter,and the CMOS stand 6-T cells are adopted to form SRAM. With the help of delay time, control logic accomplish the demand of sequential circuitry.Methods of system simulation is discussed and rusults are analyzed.The whole layout is given. At the end, the design results of the chip are summarized.Up to now, the chip is fabricating.