Design And Analysis Of The Phase-Locked Loop For DSP

With the rapid development of IC design and process, high performance and low cost are now the main challenges for SOC design. Phase-locked loop(PLL) used as clock generator on chip becomes very critical. Because of the merit of integrated easily, low power, low jitter, small phase difference error and big capture scale, the CPPLL(Charge-pump PLL) has become one of the major digital PLL product.This paper presents a third-order CPPLL used in the 16-bit fixed-point DSP. Based on the analysis of the theory of CPPLL and application requirements in the DSP, the structure and the performance specifications of the PLL are defined, and then the subcircuits are designed. During these procedures, this thesis discusses and solves the following problems:1) Optimizes the PFD(Phase and Frequency Detector) to reduce the Dead-zone and increase the bandwidth of phase detector;2) Adopts a new type of CP(Charge-Pump) with accelerated switch in source, it solve the effect of charge sharing and with high current matching accuracy;3) Adopts a second-order RC filter to reduce the output ripple, and optimizes the parameters of the filter;4) Adopts a ring VCO which consists of four stage of delay elements, each of them adopts the RS flip-flop to generate difference output. This structure reduces the power dissipation effectively and with much better performance in anti-noise;5) Design the programmable frequency divider by method of full custom. It reduces elements as much as possible and meets the different requirements in the frequency of output clock.The CPPLL is completed in SMIC 0.35um CMOS process with 5V supply voltage, the area of the chip is 502μm×476μm. Simulation results show that the PLL can operate from 2MHz to 60MHz. When the output of VCO is 20MHz, the lock time of the PLL is 12.7μs, the peak-to-peak jitter is less than 512ps, and its power dissipation is only 6.2mW, so it can fully saitisfy the requirements of the DSP clock system.At the end, this thesis creates the Verilog function model of the CPPLL in order to meet the demand of DSP system verification, and briefly presents the design of PLL IP core in future work.