The VHDL Design And Simulating Of HDB3 Encoding/Decoding

The HDB3 coding scheme is commonly used in digital baseband transmission. The HDB3 code, which has features of zero DC bias via alternating positive-negative voltage level bit by bit and no more than three continuous-zero bits, deduces the power dissipation and makes the receiving device easy to recover the clock in the transmitted code stream. In this paper, the HDB3 encoding/decoding system was designed based on VHDL. The alternative voltage level was inserted into the serial code stream when four continuous-zero bits are met. The EDA developing tool Altera Maxplus II 10.2 is utilized to carry on compiling, simulating, and verifying the exactness of designed system. Finally the application of HDB3 could be presented.