Research Of Timing Recovery Technology Of Read/Write Channels Of Hard Disk Drives

The hard disk drives can not be substituted in the near future due to its high performance and huge capability in storage. Along with the development of the epoch, higher density and faster transmission speed of the hard disk drives are needed. However, the improvement of the performance is deeply affected by read/write channels. The Partial-Response Maximum Likelihood (PRML) technology has been adopted up to the present by right of its predominant performance on anti-noise. But, to the development prospect of the PRML, the sampling frequency becomes higher, so that the request of the timing precision also becomes higher. So, the research of the high-performance timing recovery technology is urgently needed. High-performance timing recovery technology plays an important role on the reliability of the data recovery.The existing timing recovery schemes are always the synchronous phase-lock one. They are respectively the digital phase-lock scheme and the analog phase-lock scheme. For deep research of existing timing recovery technologies, a differential coefficient commutate mode timing recovery simulation model based on digital phase-lock principle and a minimum mean square error algorithm timing recovery simulation model based on analog phase-lock principle are built. The ideology of all these two models is let the phase of the local clock to be synchronous with the symbol. It has disadvantages such as the long lock time etc.For the sake of improving the performances of the timing recovery, aim at the characteristic of the PRⅣchannel, deduced a new non-data-aided timing error estimator algorithm that suits the PRⅣread/write channel with the reference on the all digital receiver technology in communication. Based on this algorithm, an open-loop asynchronous interpolated filter timing recovery simulation model has been built. The ideology of this model is to recovery the sampled data value at the right sample time use the sampled value that from the local free clock and the timing error estimator value. In this scheme, the interpolator used the Lagrange cube interpolation algorithm with the Farrow architecture, and the timing error estimator algorithm is non-data-aided algorithm with two samples per symbol. This algorithm let the hard disk drives no longer need the preamble pattern. And it also improves the convergence speed of the timing error estimator, and enormously quickens the capture speed. And it can adjust the timing error faster, and enhances the capability of anti-jamming, result the BER (Bit Error Rate) without noise being zero. And it is implemented in all digital way, convenient for integration.