A Hardware Implementation Of Lossless Data Compression Based On LZW Algorithm

People's lives are filled with data as IT improves, which results in compression technology. The lossless data compression spreads widely in fields like medical treatment, telecommunication and so on. The implementation by VLSI technology is getting more and more attention because of its speed and more powerful ability. And related research is becoming hot.This thesis deals with the design and hardware implementation of a lossless data compression based on improved LZW algorithm. First of all, according to the requirement of hardware, LZW and Huffman coding are combined. Also parallel architecture, virtual dictionary and FIFO strategy are introduced.According to the algorithm the thesis proposes a core of lossless data compression. The core uses a parallel searching strategy to speed up string searching greatly. Meanwhile, the dictionary is divided into 8 parts with different size, which reduces the memory space. The core is composed of modules realized by Verilog HDL. In the design of dictionary, a hierarchical design methodology is used, making it quite clear and concise. A configurable registers module is designed to control different functions of the core, which makes control subsystem and data processing subsystem apart and clearly. Finally a BIST module based on CRC8 checker is used, which will increase test speed and reflect DFT ideas.After the design of the core a simulation model by C language is used to prove the validity of the hardware implentmentation and the dictionary strategy chosen. Finally the compression core is simulated in Modelsim environment, and the result reveals that the hardware core can compress data correctly according to improved LZW algorithm. The Synplify is used to synthesize codes of the core at the target FPGA of Xilinx Virtex4 XC4VFX100. The result reveals that the maximum frequency is up to 175MHz, and the resource taken is also acceptable. So the total data processing ability reaches 601Mbps, about 20 times of software implementation. So the design is as good as other hardware implentmentations.