Design And Implementation Of Radiation Hardened SRAM Using Commercial Process

As the member of the family of semiconductor memory,static random access memory(SRAM) is the mostly popular one.SRAM is a necessary component in most applications such as digital signal processing,information technology and automatic control.With the rapid progress of space technology,more and more SRAMs are used in control systems of various spacecrafts and satellites.SRAM is very sensitive to single event effects,and it is the weakest part in space microprocessors. So,it is very necessary to research on the influence of single event effects on SRAM and the corresponding hardening techniques.Design and implementation of radiation hardened SRAMs using commercial process has been studied in this work.An 8Kb SRAM test chip composed of HIT,DICE and 10T cell has been designed and implemented.A SRAM radiation testing system has been designed.SEU hardening mechenism of HIT,DICE and 10T cells has been analyzed,and their general performance has been compared.Upset mechanism of the DICE cell in very deep sub-micro CMOS process is analyzed,and a novel mixed radiation hardened SRAM cell is proposed. Several small resistances are introduced in the new cell,which has remarkable SEU hardening performance over the normal DICE cell with an acceptable area cost.Layout area of the new cell increases about 85% over the normal DICE cell.Critical charge of the new cell is 1.5pC, comparing 180fC of the normal DICE cell,and the increment is about 7.3 times.A circuit design method to improve the yield and reliability has been proposed.Design principle of the redundant line/colume has been explained,the overall architecture of the new SRAM with redundant logic has been presented,and circuit implementation of the redundant line/colume has been detailed.